SMF 113-1 Hardware capacity, reporting and statistics
    • 18 Mar 2024
    • 2 Minutes to read
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    SMF 113-1 Hardware capacity, reporting and statistics

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    Article summary

    Introduction

    Fields

    Stored in hisData

    SMF FieldDB Column nameDescriptionUnit
    recTypeValue is always 0
    SMF113IntervalStartstartTimeInterval start time
    SMF113IntervalEndendTimeInterval end time
    secondsDifference between endTime and startTime
    SMF113SIDsidSystem identification
    SMF113_1_MachType
    SMF113_1_SeqCode
    cecNametypeNum-seqNum
    SMF113_1_MachTypetypeNumThe machine type
    SMF113_1_MachModelmodelNumThe machine model
    plant
    SMF113_1_SeqCodeseqNumThe machine sequence code
    SMF113PNMprdNameProduct name
    SMF113OSLmvsLevelMVS product level
    SMF113_1_CpuProcClasscpuTypeThe processor type for which the hardware event counters are recorded
    SMF113_1_CpuIdcpuidProcessor ID for which the hardware counters are recorded
    SMF113_1_CoreIdcoreIdCore ID for which the hardware event counters are recorded
    lsprWkldLSPR Workload match based on L1MP and RNI
    SMF113_1_CtrVersion2counterVsSecond counter version number
    rni
    l1MisPctCache L1 misses per total instructions
    fromL2PctNumber of cache misses from L2 cache
    fromL3PctNumberof cache misses from L3 cache
    fromL4PctNumber of cache misses from L4 cache
    fromL4rPctNumber of cache misses from L4-remote cache
    fromMemPctNumber of cache misses from Memory
    cpuBusyPctCPU utilization
    usrInstrPctPercent of problem-state instructions
    SMF113_1_CpuSpeedcpuSpeedProcessor speed for which the event counters are recordedcycles/microsecond
    totCpiTotal cycles per instructions
    wklMipsCapCPU capacity for my workloadMIPS
    userCpiAverage cycles per instructions in problem-state
    netCpiCannot calculate the overhead
    overCpiOverhead cycles per instructions due to TLB and cache misses
    l1MisCpiAverage number of cycles per cache misses
    tlbMisCpi
    totMipsMillions instruction execution per second
    totCpuTimeLpar CPUmillisecond
    usrCpuTimeuser-mode CPUmillisecond
    l1MisTimeTotal (I+D) cache miss penalty time
    instrCountTotal million-instruction execution
    cycleCountTotal cycles executing instructionsmillion
    usrInstrCntUser-mode million-instruction execution
    l1MissesCache L1 directory write instructions
    tlbMissesTLB miss countmillion
    tlbMisRateTLB missmillion/second
    userCyclesTotal cycles executing instructions in problem-state modemillion
    penaltCyclesCache L1 misses penalty cycles
    overCyclesOverhead cycles due to TLB and cache misses
    tlbCyclesD-TLB + I-TLB miss cycles
    invIcachePctPercent of I-cache L1 writes from On-chip L3 (SIIS) from all I-cache Level-1 writes
    excDcachePctPromote to Exclusive percentage
    crptTotalCntPRNG + SHA + DEA + AES function count
    crptBusyCntPRNG + SHA + DEA + AES blocked function count
    crptPrngCntNumber of pseudo-number-generation functions executed
    crptShaCntNumber of SHA cryptografic functions executed
    crptDeaCntNumber of DEA cryptografic functions executed
    crptAesCntNumber of AES cryptografic functions executed
    crptTotTimePRNG + SHA + DEA + AES cycles
    crptWaitTimePRNG + SHA + DEA + AES blocked cycles
    crptPrngTimeTotal cput time spent on pseudo-number-generation function executions
    crptShaTimeTotal cput time spent on SHA function executions
    crptDeaTimeTotal cput time spent on DEA function executions
    crptAesTimeTotal cput time spent on AES function executions
    crptPrngCpiAverage number of cpu cycles to execute pseudo-number-generation functions
    crptShaCpiAverage number of cpu cycles to SHA functions
    crptDeaCpiAverage number of cpu cycles to DEA functions
    crptAesCpiAverage number of cpu cycles to AES functions
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