---
title: "SMF 113-1 Hardware capacity, reporting and statistics"
slug: "smf-113-1-hardware-capacity-reporting-and-statistics"
updated: 2024-03-18T16:33:18Z
published: 2024-03-18T16:33:18Z
canonical: "docs.zetaly.io/smf-113-1-hardware-capacity-reporting-and-statistics"
---

> ## Documentation Index
> Fetch the complete documentation index at: https://docs.zetaly.io/llms.txt
> Use this file to discover all available pages before exploring further.

# SMF 113-1 Hardware capacity, reporting and statistics

## Introduction

## Fields

Stored in hisData

| SMF Field | DB Column name | Description | Unit |
| --- | --- | --- | --- |
|  | recType | Value is always 0 |  |
| SMF113IntervalStart | startTime | Interval start time |  |
| SMF113IntervalEnd | endTime | Interval end time |  |
|  | seconds | Difference between endTime and startTime |  |
| SMF113SID | sid | System identification |  |
| SMF113_1_MachType SMF113_1_SeqCode | cecName | typeNum-seqNum |  |
| SMF113_1_MachType | typeNum | The machine type |  |
| SMF113_1_MachModel | modelNum | The machine model |  |
|  | plant |  |  |
| SMF113_1_SeqCode | seqNum | The machine sequence code |  |
| SMF113PNM | prdName | Product name |  |
| SMF113OSL | mvsLevel | MVS product level |  |
| SMF113_1_CpuProcClass | cpuType | The processor type for which the hardware event counters are recorded |  |
| SMF113_1_CpuId | cpuid | Processor ID for which the hardware counters are recorded |  |
| SMF113_1_CoreId | coreId | Core ID for which the hardware event counters are recorded |  |
|  | lsprWkld | LSPR Workload match based on L1MP and RNI |  |
| SMF113_1_CtrVersion2 | counterVs | Second counter version number |  |
|  | rni |  |  |
|  | l1MisPct | Cache L1 misses per total instructions |  |
|  | fromL2Pct | Number of cache misses from L2 cache |  |
|  | fromL3Pct | Numberof cache misses from L3 cache |  |
|  | fromL4Pct | Number of cache misses from L4 cache |  |
|  | fromL4rPct | Number of cache misses from L4-remote cache |  |
|  | fromMemPct | Number of cache misses from Memory |  |
|  | cpuBusyPct | CPU utilization |  |
|  | usrInstrPct | Percent of problem-state instructions |  |
| SMF113_1_CpuSpeed | cpuSpeed | Processor speed for which the event counters are recorded | cycles/microsecond |
|  | totCpi | Total cycles per instructions |  |
|  | wklMipsCap | CPU capacity for my workload | MIPS |
|  | userCpi | Average cycles per instructions in problem-state |  |
|  | netCpi | Cannot calculate the overhead |  |
|  | overCpi | Overhead cycles per instructions due to TLB and cache misses |  |
|  | l1MisCpi | Average number of cycles per cache misses |  |
|  | tlbMisCpi |  |  |
|  | totMips | Millions instruction execution per second |  |
|  | totCpuTime | Lpar CPU | millisecond |
|  | usrCpuTime | user-mode CPU | millisecond |
|  | l1MisTime | Total (I+D) cache miss penalty time |  |
|  | instrCount | Total million-instruction execution |  |
|  | cycleCount | Total cycles executing instructions | million |
|  | usrInstrCnt | User-mode million-instruction execution |  |
|  | l1Misses | Cache L1 directory write instructions |  |
|  | tlbMisses | TLB miss count | million |
|  | tlbMisRate | TLB miss | million/second |
|  | userCycles | Total cycles executing instructions in problem-state mode | million |
|  | penaltCycles | Cache L1 misses penalty cycles |  |
|  | overCycles | Overhead cycles due to TLB and cache misses |  |
|  | tlbCycles | D-TLB + I-TLB miss cycles |  |
|  | invIcachePct | Percent of I-cache L1 writes from On-chip L3 (SIIS) from all I-cache Level-1 writes |  |
|  | excDcachePct | Promote to Exclusive percentage |  |
|  | crptTotalCnt | PRNG + SHA + DEA + AES function count |  |
|  | crptBusyCnt | PRNG + SHA + DEA + AES blocked function count |  |
|  | crptPrngCnt | Number of pseudo-number-generation functions executed |  |
|  | crptShaCnt | Number of SHA cryptografic functions executed |  |
|  | crptDeaCnt | Number of DEA cryptografic functions executed |  |
|  | crptAesCnt | Number of AES cryptografic functions executed |  |
|  | crptTotTime | PRNG + SHA + DEA + AES cycles |  |
|  | crptWaitTime | PRNG + SHA + DEA + AES blocked cycles |  |
|  | crptPrngTime | Total cput time spent on pseudo-number-generation function executions |  |
|  | crptShaTime | Total cput time spent on SHA function executions |  |
|  | crptDeaTime | Total cput time spent on DEA function executions |  |
|  | crptAesTime | Total cput time spent on AES function executions |  |
|  | crptPrngCpi | Average number of cpu cycles to execute pseudo-number-generation functions |  |
|  | crptShaCpi | Average number of cpu cycles to SHA functions |  |
|  | crptDeaCpi | Average number of cpu cycles to DEA functions |  |
|  | crptAesCpi | Average number of cpu cycles to AES functions |  |
|  | actionId |  |  |